Area scaling of SRAM (Static Random Access Memory) bit-cell is limited by read stability of an SRAM bit-cell. The conventional method to address SRAM read margin issue is to apply circuit assist technique by under driving word-line (WL). In this technique, WL voltage is lowered which makes the pull-down transistors of the SRAM bit-cell stronger than the access transistors (i.e., pass-gates). The write assist circuit allows the SRAM bit-cell to operate at a lower supply voltage while improving read margin. Lowering WL voltage, however, reduces bit-cell read current and degrades the performance of the SRAM bit-cell during low-voltage operation. For example, as WL voltage is lowered, the access transistors exhibit higher resistance which translates to lower SRAM performance. The circuit assist technique limits the SRAM design space for a designer because the designer is limited to trading off performance of the SRAM bit-cell for higher SRAM density or vice versa.